Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs

Abstract

Vertical transistors are one of the promising alternatives to standard lateral device structures in future technologies due to benefits in terms of reduced footprint and feasibility of fabrication of hetero junction structures. While such device-level benefits have been widely explored, the circuit and layout-level implications of vertical transistors require further analysis. In this work, we carry out a systematic layout and circuit analysis for 20nm vertical transistors, namely symmetrical vertical MOSFET and asymmetrical hetero junction tunnel FET (HTFET), and present a detailed comparison with 20nm Fin FETs. Our analysis clearly outlines the differences from the perspective of layouts and the performance/power of standard cells. The absence of width quantization in vertical FETs and steep switching characteristics in HTFETs result in larger drive strengths compared to Fin FETs. However, for high fan-in cells, vertical transistors show area overheads due to infeasibility of contact sharing in parallel and series transistors. For each type of device, we synthesized a 32-bit carry look ahead adder and compared energy, delay and area, taking into account layout differences due to the device structures. Our analysis shows that in spite of area overhead for some cells, high drive-strength in HTFET cells brings advantages in both area and energy over both Fin FETs and vertical MOSFETs at VDD < 0.6V.