Comparative study and analysis of area and power parameters for hardware multipliers

Abstract

This paper involves the comparative study and analysis of area and power parameters for hardware multipliers namely, Booth Multiplier, Wallace Tree Multiplier, Booth-encoded Wallace Tree Multiplier and Vedic Multiplier. The various advantages and disadvantages of these multipliers are analyzed in terms of their performance parameters using design vision tool from Synopsys, Inc. The tool utilizes 90 nanometer technology file SAED_SDK90nm to design and study the circuitry at generic technology level and gate level. The algorithms of these multipliers are coded to hardware description language (HDL) programming. The net list generates the area and power report during the process of gate level synthesis.