Comparative Analysis of Electrical Performance on Coreless and Standard Flip-Chip Substrate

Abstract

In recent years, more and more devices are designed by high-performance flip-chip ball grid array (FCBGA) packages due to the requirement on large number of I/O pads, small pitch, and high operation frequency of ASIC. Many studies were done on FCBGA packages. Some of these works were focused on thinner structures. In the study of this paper, our targets will be focused on the coreless and standard FCBGA cases. By directly replacing the BT-core of the standard substrate with a thinner build-up dielectric layer, the coreless design is a good choice to decrease the cost. This replacement makes some differences between the standard thick BT-core and the new thinner build-up substrates. Our study analyzes the electrical performance caused by these differences. With the simulation approach, the analyses include the power integrity (PI) and signal integrity (SI) issues in frequency and time domains on both coreless and standard substrates. In the final results, we found that the coreless substrates could get a better electrical performance, for examples, the smaller coupling between the signal nets, the lower impedance of the power delivery system. The results from these analyses could give a useful reference for chip designers while they make a decision on package.