Finite Element Modeling Methodology for Monotonic Bend Test of Flip-Chip BGA Package

Abstract

This paper presents a finite element modeling methodology to predict failure during four-point monotonic bend test of flip-chip ball grid array (FCBGA) packages mounted on printed circuit boards (PCBs). Monotonic bend tests are conducted to failure at approximately 4 mm/sec according to IPC/JEDEC-9702 and the strain is monitored by mounted strain gauges. Test conditions are specified through displacement boundary conditions. Models are validated with displacement and strain. We propose a failure criterion based on the typical failure location and assume it to be a material property. Three test vehicles, one single die FCBGA package and two chip-on-wafer-on-substrate (CoWoS) FCBGA packages are used for validation; all test vehicles are exposed die with stiffener ring packages. From these test vehicles, failure occurs most by cratering the board side pad. Using the proposed methodology, the failure strain for a 3.175mm thick Megtron6 board is calculated to be 5975 μstrain without via-in- pad plated over (VIPPO) and 8130 with VIPPO. The failure criterion is then used to study the effect of design parameters on monotonic bend performance. A parametric study finds when the PCB is thick, board parameters are the most important, BGA parameters are next most important, and most package level parameters have little impact.