Abstract
Traditional full chip electrostatic discharge (ESD) protection circuits consumes a large amount of chip area. To resolve this problem, a novel three-terminal compact and compound SCR (CCSCR) is proposed. The proposed CCSCR employs intrinsic parasitic SCRs and ESD diodes as main ESD discharge paths to independently implement full chip ESD protection, which can greatly reduce area consumption and achieve high ESD robustness. The TCAD simulation indicates that the proposed CCSCR has a low trigger voltage and a high holding voltage. In addition, RC detection circuit is also introduced into CCSCR to further reduce the trigger voltage and improve the holding voltage, which makes CCSCR more efficient as a candidate ESD device in nanoscale CMOS technology.
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