Abstract
A study of process-device-layout co-design procedure for full-chip electrostatic discharge (ESD) protection design for high-voltage (HV) ICs in a Bipolar-CMOS-DMOS (BCD) technology is reported. The full-chip ESD protection scheme includes I/O and power clamp ESD protection. Co-design using mixed-mode TCAD ESD simulation technique ensures design optimization and prediction. Test result confirms full-chip ESD protection of at least 4.5K V.
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