Combating Bit Errors From Stuck Cells in Flash Memory Using Novel Information Theory Techniques

Abstract

Recently, low-density parity-check (LDPC) codes have been successfully deployed in NAND Flash memory based Solid State Drives. As Flash memory scales and has now advanced from two-dimensional architectures to three-dimensional ones, defects in the form of stuck cells have increased. As far as algebraic codes like BCH are concerned, the errors from the stuck cells impact it just as any other errors. However, for LDPC codes, the stuck cells are three times as detrimental compared to other soft errors. In this work, we first propose to flag the bits read from stuck cells as erasures. It turns out that it is better that the LDPC code be informed that bits are lost as erasures rather than being erroneously informed with high confidence about the stuck cells’ values. This erasures and errors correction improves the performance of the LDPC code. To realize further improvements in performance, we propose a method to reduce the raw bit error rate due to stuck cells in NAND Flash memory. We propose a divide and conquer strategy whereby we do not use all the available redundancy for LDPC parity. Instead we use some redundancy to first shape the data using sectionalized Flip and Write (FNW) so that it matches with the stuck cells read with high probability. This reduces the bit errors due to stuck cells. The residual small number of errors due to stuck cells needs to be corrected by the LDPC code. Both of the proposals have been validated with simulation results based on a one kilobyte information block encoded for an LDPC code of rate 0.9. Errors and erasures decoding, and sectionalized FNW result in 1.92× and 1.94× raw bit error gains for soft-decision decoding, respectively.