A concatenation scheme of LDPC codes and source codes for flash memories

Qin Huang,Mu Zhang,Zulin Wang,Shangzhi Pan

doi:10.1186/1687-6180-2012-208

Abstract

Abstract Recently, low-density parity-check (LDPC) codes have been applied in flash memories to correct errors. However, as verified in this article, their performance degrades rapidly as the number of stuck cells increases. Thus, this paper presents a concatenation reliability scheme of LDPC codes and source codes, which aims to improve the performance of LDPC codes for flash memories with stuck cells. In this scheme, the locations of stuck cells is recorded by source codes in the write process such that erasures rather than wrong log-likelihood ratios on these cells are given in the read process. Then, LDPC codes correct these erasures and soft errors caused by cell-to-cell interferences. The analyses of channel capacity and compression rates of source codes with side information show that the memory cost of the proposed scheme is moderately low. Simulation results verify that the proposed scheme outperforms the traditional scheme with only LDPC codes.

Highlights

In flash memories, as programming and erasure (P/E) cycles increase, some cells may be stuck at a voltage level not related to the data being written in, resulting in stuck cells or defective memory cells [1,2]
A class of hard-decision decoding error correction codes (ECC), Bose Chaudhuri Hocquenghem (BCH) codes, are employed to correct such stuck errors caused by stuck cells as well as soft errors [3,4], induced by cell-to-cell interferences
The proposed concatenation scheme Until now only ECCs, e.g., BCH codes or low-density parity-check (LDPC) codes, are used to correct errors in practice, since the additive white Gaussian noise (AWGN) sub-channel dominants the performance in the early stage of flash memories

Summary

Introduction

As programming and erasure (P/E) cycles increase, some cells may be stuck at a voltage level not related to the data being written in, resulting in stuck cells or defective memory cells [1,2]. We present a concatenation reliability scheme of LDPC codes and source codes to alleviate the performance degradation. When the controller is writing data into flash memories, it is designed to detect stuck cells. The locations of these stuck cells are compressed by source codes with side information to efficiently reduce the memory cost. We compare the proposed concatenation scheme with the traditional one from the angle of error performance and memory cost. On one hand, it can significantly outperforms the traditional one, since it removes the wrong LLRs for LDPC decoders.

Background

Findings

Conclusion