Abstract
Through-silicon via (TSV), an emerging technology for 3D IC manufacturing, involves fabrication of vertical vias through the wafers. The two methods commonly used involve "via-first" and "via-last" process flows. While the via-last approach appears to be relatively simple with minimum impact to circuit layout, the via-first scheme may ultimately offer more benefits by enabling a higher density of I/O's. This paper describes the rapid progress made in the process integration of CMP for TSV, to offer unique advantages especially in the via-first approach where planarity is critical. In addition, with backside polishing after wafer thinning, the CMP process ensures a smooth surface finish for bonding and provide extra process knobs to correct the non-uniformity in via depths caused by preceding via etch and silicon grinding processes.
Published Version
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