CMOS Sensor Arrays for High Resolution Die Stress Mapping in Packaged Integrated Circuits

Abstract

This paper reports the design, calibration and application of multiplexed arrays of piezoresistive field-effect transistor stress sensors fabricated in a standard complementary-metal-oxide semiconductor (CMOS) process. Two complementary arrays of 256-current mirror sensor cells provide high spatial density stress mapping with approximately 300 pts/mm2 using only a 1.5 μm process. The arrays are sequentially scanned by an on-chip counter, producing efficient stress measurement, and the sensors resolve normal and shear stresses on the surface of the die with resolution below 1 MPa. The CMOS sensor chips have been used to map stress over a large portion of the die in chip-on-beam and encapsulated chip-on-beam samples, as well as a ceramic dual-in-line package with its cavity filled with underfill material. Finite-element simulation results correlate well with the measured stress distributions. The experimental results from these chips are used to validate finite-element simulation models, and the array designs can be used as subarrays in much larger test chips.