CMOS Scaling Analysis based on ITRS Roadmap by Three-dimensional Mixed-mode Device Simulation

Abstract

In this paper, the circuit performances such as circuit delay, RF characteristics and SRAM static noise margin are presented. These analyses are performed by threedimensional device simulation using Mixed-mode option. The benefit of circuit delay in scaling will be maintained by introducing new structure (SOI, multi-gate), material (silicide, metal gate) and strain effect. However, concerning with SRAM SNM, it becomes already difficult to operate even in 65nm node.