CMOS quaternary logic encoder-decoder circuits

Abstract

Abstract A binary-to-quaternary encoder and quaternary-to-binary decoder circuit pair is proposed. Two non-zero voltage levels and two pulse durations are used to define a 4-valued logic scheme. We have simulated the encoder and decoder circuits using model parameters for standard CMOS technology and minimum geometry devices. An average amplitude decoder delay of 10 ns has been recorded using Hspice simulator transient analysis. Width decoder delays of respectively 50 and 75 ns for the rising and the trailing transitions of the encoded signal have been recorded. Since only two voltage levels have to be distinguished, the noise immunity and logic level tolerances are improved, compared to the case where four different voltage levels have to be distinguished using existing approaches. This improvement is achieved at the expense of the greater bandwidth needed for transmission of signals using the proposed scheme.