CMOS Performance Scaling

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CMOS transistors have been scaling exponentially in the past two decades and the intrinsic device performance has followed a commensurate scaling trend. Prior to the 90-nm node, mere shrinking of the device dimensions, following Dennard’s scaling theory, was sufficient to guarantee increased device performance; beyond the 90-nm node, new innovations were necessary to continue the historical performance scaling trend. Strain engineering and high-k/metal gate technologies were the two major innovations that made the commensurate performance scaling in the past decade possible. However, it appears that new device structures and performance boosters will continue to be the need of the future. This chapter provides a basic overview of MOSFET scaling trend, followed by a discussion of MOSFET operation in deca-nanometer scale based on the so-called virtual source injection model. A simple analytical model for transistor I–V characteristics and intrinsic transistor delay is provided and used to quantify the historical trends of MOSFET performance scaling. Carrier velocity is shown to be the main driver for the continued MOSFET performance increase. Finally, the prospect of velocity increase is reviewed for strained Si, Ge, and compound semiconductors.