CMOS low noise amplifier designs for 5.8 GHz dedicated short‐range communications applications

Abstract

ABSTRACTThis article presents two low noise amplifier (LNA) designs in 5.8 GHz using 0.18 μm CMOS technology, for dedicated short‐range communications (DSRC) applications. The source degenerate inductor is utilized for the cascode configuration with and without the mutual coupling from the gate inductor, to show the compromise between chip size and noise figure, where the mutual inductor reduces the chip area with a little increase of noise figure. To improve the receiver dynamic ranges of the two designed LNAs, the gain‐control function is added by the bias current bleeding at the common‐gate stage of the cascode configuration. The measured results accomplish 10.9 dB in gain and 3.6 dB in noise figure with −5 dBm of input 1 dB gain compression point (P1dB) for the design without mutual inductor, and 11.2 dB in gain and 4.4 dB in noise figure with −5 dBm input P1dB for the design with mutual inductor, while the chips occupy 0.42 mm2 and 0.36 mm2, respectively. These LNA designs can fulfill the requirements of DSRC applications. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2524–2529, 2015