CMOS Differential Logic Family With Conditional Operation for Low-Power Application

Abstract

In this paper, a set of CMOS differential logic circuits are introduced for use in low-power application. They perform a conditional operation for statistical power reduction during logic operation. The self-precharged version of the logic family provides additional power saving by allowing the use of a small-swing clock. Synchronous counters and bidirectional shift registers were designed in a 0.18-mum CMOS process technology to assess the performance of the proposed technique. The measurement results indicate that the counter with the proposed logic family achieves 50% power reduction compared with that of the conventional logic family. They also indicate that the shift registers with the proposed technique achieve 44%-63% power reduction at a typical switching activity of 0.25.