Abstract

Over that past four decades, the trend in the electronic industry has been to increase functional density and system performance, and to decrease cost with time. This has largely been made possible by the down-scaling of device dimensions, increased integration densities and improved fabrication technologies. However, the continued down-scaling of devices and interconnections is expected to meet technological and physical limitations, due to, for example, proper device operation or heat removal considerations. In fact, the continued reduction of the device dimensions (for example field-effect transistors, FETs), will not lead to improvements beyond a certain short channel length because of parasitic effects, saturation velocity effects, and high field effects, and because delays at the system level will be dominated by interconnection time constants (which do not scale with geometries) and problems associated with the increasing interconnection current densities due to their decreasing cross-sectional areas. Rather, improvements in the speed of high performance systems demand greater increases in device density than device speed, but this in turn leads to power density limitations. Thus, unless novel chip architectures, creative device and process designs, and revolutionary devices such as quantum-based devices are used, other means for achieving high speed/high density integrated circuits that are not limited by interconnection delays must be found. One approach to achieving high performance circuits and systems is to operate them at cryogenic temperatures, and it is this approach that is described in this chapter.

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