Abstract

Scaling of MOSFETs has led to the continued improvement in both device speed and density of CMOS technology according to the Moore's Law [1]. However, the power density also increases with the device density. Voltage scaling is crucial to reduce the power density with dimensional scaling. In this work, we address the key issue pertaining to the choice of channel materials to effectively scale V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> . The I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> of DG-UTB devices with channel materials from group IV (Ge) and III-V (GaSb, InAs, In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</inf> Sb) were compared against the high performance (HP) logic requirements in ITRS [2], since these materials were reported to have higher carrier mobilities [3], [4]. DG-UTB FETs with 2D materials were compared against the low operating power (LOP) logic requirements in ITRS. The 2D materials comprise the 2D-transition metal dichalcogenides (TMDs) [5] and hydrogenated silicene (silicane) and germanene (germanane). These 2D materials were considered since they have larger band gaps and effective masses which suppress the leakage current due to the band-to-band tunnelling. Moreover, 2D materials with atomically thin bodies have excellent electrostatic integrity which minimizes the short channel effects. DG-UTB FETs with silicon channels were included in the analysis for benchmarking purposes.

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