Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method

Abstract

Mathematically the most difficult partitioning problem–packaging–is being considered. Its purpose is to minimize a number of partitions and to satisfy the constraints on the number of constituent elements and external nets. To solve the problem, the Optimal Circuit Reduction Method, suggested by R. Bazylevych is being used. The optimal reduction tree to reflect the hierarchical entrance of smaller clusters into bigger ones is being built for the first step. At the second step we select one or more tree vertices which better meet the given constraints and are the first partitions generated from. After creating every new partition we eliminate its elements from the circuit and repeat the procedure to complete all partitions. During the last stage optimization strategies to exchange some elements between the partitions are being used. Better or equivalent results among known tests confirm the effectiveness of this method.