Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

Abstract

In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with $L_{\mathrm{ eff}}= 36$ nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for $f_{T}$ , $f_{\mathrm {\mathrm {MAX}}}$ , and NFmin at 26 GHz up to ~13%, ~24%, and ~18% compared with the reference layout scheme, respectively.