Extraction procedure for MOS structure fringing gate capacitance components

Abstract

The microelectronics industry has progressed astonishingly along several decades, thanks to the MOS transistor shrinkage. However, the parasitic gate capacitance becomes an important concern for device behavior optimization in the nanometric range. The fringing parasitic gate capacitance exhibits weaker channel length dependence than the intrinsic counterpart. For this reason, the relative weight of the parasitic gate capacitance will be more significant for future technology nodes. In this contribution, an extraction procedure to determine the main fringing components of a simple MOS structure is presented. Numerical simulations were used to validate the presented methodology. Finally, results indicate that for sub-25 nm gate electrode length, normalized total fringing capacitance associated to the transistor width is greater than the intrinsic counterpart.