Circuit design in nano-scale CMOS technologies

Abstract

The relentless pursuit of Moore's law by semiconductor industry has led the feature size of CMOS transistor scaled well into nano-scale regime. Deeply scaled CMOS technologies have created many new challenges for circuit design, including device variation and shrinking voltage head-room in analog circuits. In this presentation, an overview of today's technology landscape will be presented first, including major innovations that have kept the Moore's law continue. Then the focus of the talk will be on how to address the scaling challenges with novel circuit design techniques, ranging from low-power and high-performance digital to embedded memory, analog and mixed-signal circuits. Some real design examples will be used to illustrated the new design concepts that help to overcome the scaling challenges.