Circuit Design in Nano-Scale CMOS Technologies

Abstract

CMOS technology scaling has followed Moore's law well into the nano-scale regime now. The technology scaling is no longer just about geometric reduction but more about innovation in the use of new materials and transistor architectures. Relentless feature size reduction along with the innovations in transistor architecture and new material have created both challenges and opportunities for circuit designers to fully realize the technology scaling benefits. In this talk, an overview on the technology scaling will first be presented. The talk will then explore many advanced circuit design techniques that are key to achieve product-level scaling benefits. It will start with SRAMs, the work-horse for embedded memories. The state-of-the-art read-write-assist (RWA) techniques in SRAMs will be discussed for achieving adequate margins for low-voltage operation. Analog and mixed signal (AMS) circuits are long considered not scalable due to many unique design requirements and process sensitivities. In this talk, several novel digital-assist techniques are explored to illustrate how they can help achieve excellent power, performance, and area scaling in some common AMS circuits such as phase-lock-loop (PLL) and high-speed serial IO. Adaptive design concept has become a focal point in advanced circuits today to augment the process variations. A couple of design examples will be given to demonstrate the benefits of these advanced circuit techniques. To further improve system-level performance, more intelligent integration schemes are becoming more important. Again, real product examples, including integrated-voltage-regulator and in-package-memory, will be given on how they can help address the power/performance challenges at system-level. In conclusion, as CMOS technology scaling continues, novel circuit topologies and integration schemes will play an increasingly more important role in driving the power and performance scaling for future products.