Circuit design in nano-scale CMOS era

Abstract

Moore's law has driven today's CMOS technology well into the nano-scale regime. For over four decades, the relentless technology scaling has been the main growth engine for the semiconductor industry in bringing out ever-increasing performance to the end-user while lowering product cost. But the miniaturization of CMOS transistor has led to many new challenges and increasing difficulties in achieving robust circuit design to meet power and performance needs along with high-volume manufacturing (HVM) requirements. It is particularly challenging in designing embedded memory and analog circuits on a leading edge logic process in which the transistor-induced variations pose a growing hurdle in achieving the robustness of the design as the technology scaling continues. Technology and design co-optimization has become essential for the success in developing future VLSI circuits.In this talk, the state of current technology scaling trend along with key process innovations will be first discussed, along with their impacts on fundamental circuit design. The presentation will then focus on the scaling challenges facing today's VLSI circuits, including overall power management, voltage scaling for on-die SRAM design, and robustness of key analog circuit blocks for the state-of-the-art CPU and logic applications. Innovative design solutions along with process optimization will be thoroughly discussed as examples on how to achieve optimal scaling benefits while meeting the HVM requirements. The future direction in CMOS circuit design will then be discussed in light of continuous technology scaling.