Circuit and technique for characterizing switching delay history effects in silicon-on-insulator logic gates

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The delay of a partially depleted silicon-on-insulator complementary metal oxide semiconductor (MOS) logic gate can vary by 10% or more due to history effects. We describe and demonstrate a circuit and measurement technique with which one can measure history effects dominated by either the output rising (pMOS) or output falling (nMOS) characteristics of a multiple-input silicon-on-insulator gate. To precondition the floating-body voltages, any combination of inputs and number of switching events, arbitrarily configured with respect to timing and sequence, may precede an event to be measured.