Chips Classification for Suppressing Transient Current Imbalance of Parallel-Connected Silicon Carbide MOSFETs

Abstract

This article addresses the influence of parameters spread on transient current distribution among parallel-connected silicon carbide (SiC) mosfet s and proposes a chips classification method to suppress current imbalance. A comprehensive comparison of parameter spread between silicon (Si) and SiC mosfet s is first presented. Then, a new classification criterion, referred to in this article as a distance coefficient of transfer curves (DCTC), is proposed to characterize device spread. In addition, the sensitivity analysis of transient current imbalance (TCI) to device spread is carried out. It is found that TCI increases almost linearly with increasing DCTC. Furthermore, a hierarchical cluster algorithm is developed to achieve an automated chips classification for multiple devices intended for paralleled application. This algorithm may as well facilitate the chip selection process for multiple-chip power module packaging. Moreover, the influence of operating temperature on classification is also discussed. It should be noted that chips classification needs to consider real application conditions and package parasitic. Finally, a test bench with a round layout is designed, to keep circuit layout asymmetry to a minimum, and used to experimentally verify the performance of the classification method. The experimental results validate the effectiveness of the proposed classification method for suppressing TCI.