Abstract
The trapping of charge carriers in very thin SiOx/ZrO2 and SiOx/TiO2 gate dielectric stacks during constant gate voltage stress of metal–oxide–semiconductor capacitors has been investigated. The increase of the gate current density observed during the gate voltage stress has been analyzed, taking into account both the buildup of charges in the layer as well as the stress-induced leakage current contribution. From data analysis, the cross section of traps generated during the electrical stress is estimated. It is suggested that these traps are probably ZrOH and TiOH neutral centers that are related to the breaking of bridging O bonds by mobile H+ protons followed by the trapping of these protons at ZrO or TiO sites.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.