Model for the trap-assisted tunnelling current through very thinSiO2/ZrO2 gate dielectric stacks

Abstract

A model for the tunnelling current through SiO2/ZrO2 gatedielectric stacks is presented, taking into account the trap-assistedtunnelling process through traps located below the conduction band of theZrO2 layer. It is shown that the experimental results observed onn-Si/SiO2/ZrO2/Au capacitors at low voltage can only be reproducedwith realistic values of the physical parameters when the trap-assistedcontribution to the tunnelling current is included. The increase in thegate current density observed in a SiO2/ZrO2 gate stack duringconstant gate voltage stress was investigated next. It is shown that thestress-induced leakage current can also be very well explained by thetrap-assisted tunnelling model, taking into account the increase in thetrap density Nt with stress time. It is found that Nt varies as apower law with the stress time in the ZrO2 layer, as in ultra-thinthermal SiO2 layers. It is suggested that the same degradation mechanismcould occur in these different materials, namely H+ generation andtransport through the gate dielectric during the electrical stress,resulting in bond breaking and neutral trap generation.