Abstract
We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T phy) hafnium oxide (HfO 2)/silicon dioxide (SiO 2) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).
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