Direct tunneling stress-induced leakage current in ultrathin HfO2∕SiO2 gate dielectric stacks

Abstract

The conduction mechanism(s) and behavior of direct tunneling stress-induced leakage current (SILC) through ultrathin hafnium oxide (HfO2)/silicon dioxide (SiO2) dual layer gate stack in metal-oxide-semiconductor (MOS) devices have been experimentally investigated in-depth. Both transient and steady-state SILCs have been studied after constant voltage stress (CVS) and constant current stress (CCS) in n-MOS capacitors with negative bias on the tantalum nitride (TaN) gate. The present report clearly indicates that the observed steady-state SILC is due to assisted tunneling via both monoenergetic trapped positive charges and neutral electron traps generated in the HfO2 layer during either CVS or CCS. SILC measured immediately after stress decays slowly due to tunnel detrapping of stress-induced trapped holes in the HfO2 layer. Furthermore, the mechanisms for stress-induced charge carrier generation/trapping and trap creation in the dielectric have been discussed. Our analysis also shows that CVS degrades the dielectric integrity more severely than CCS in the 4.2nm physically thick HfO2∕SiO2 stack.