Abstract
Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm were fabricated using 0.35um SiGe BiCMOS. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances as well as their behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration in the fuse link. A T0 analysis of CoSi shows link resistance scaling and temperature characteristics. Discrete eFuses were also subjected to 100ns Transmission Line Pulse (TLP) to compare ESD handling and robustness, and the associated MOSFET circuitry characterized for safe operating area (SOA) under DC and pulsed conditions. The analysis was expanded to look at the difference between the blow FET DC (reflected in the device models) and the pulsed FET (TLP) behavior (not captured in Design Kits). This work demonstrates the compatibility of electrically programmable fuse (eFuse) technology across a range of process technology nodes, as well as its robustness in high reliability applications.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
