A simple but effective ESD robustness improvement for NMOS transistors used in I/O pads

Abstract

This paper presents a simple but effective way to improve an NMOS transistor's ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper. Both TLP (Transmission Line Pulse) measurements and HBM (Human Body Model) ESD tests are performed to assess the weakest area of NMOS regarding ESD robustness. Finally this NMOS ESD robustness is doubled by changing only one mask (without introducing any process or design change). The change offers potential for all NMOS transistors used in the same configuration of ESD protection circuits.