Characterization of advanced gate stacks for Si CMOS by electron energy-loss spectroscopy in scanning transmission electron microscopy

Abstract

Novel metal oxide films and new metal gates are currently being developed for future generations of Si based field-effect transistors as the SiO 2 gate dielectric and polycrystalline Si gate electrode are reaching scaling limits. These gate stacks are often comprised of sub-nanometer layers. Device properties are increasingly controlled by the complex structure and chemistry of interfaces between the layers. Electron energy-loss spectroscopy (EELS) in scanning transmission electron microscopy (STEM) is capable of providing insights into interfacial chemistry and local atomic structure with a spatial resolution unmatched by any other technique. Using gate stacks with Hf-silicate dielectrics as examples, we demonstrate the capabilities of STEM/EELS for analyzing the interfacial chemistry of novel gate stacks. We show that a priori unknown reaction layers of a few Å thickness can be detected and identified even in the presence of substantial interfacial roughness that may obscure such layers in a high-resolution image. We discuss some experimental aspects of STEM/EELS chemical profiling applied to gate stacks and the factors affecting the interpretation. In particular, the effects of interfacial roughness, beam spreading, elemental analysis in a heavily scattering matrix, and the interpretation of the EELS core-loss fine-structures from ultrathin layers are discussed.