Abstract
La-based high-k oxides as gate dielectrics are promising for the complementary metal–oxide–semiconductor (CMOS) devices. We investigated the chemical compositions across a TaN/LaSiO/Si gate stack at sub-nanometer scale with electron energy loss spectroscopy (EELS) mapping, Z-contrast imaging, high-resolution transmission electron microscopy (HRTEM) imaging, and other tools. The interfaces in the gate stack were shown to maintain their integrity even after post annealing. The alloying between La2O3 and SiO2 to form LaSiO depended on the annealing conditions. To the as-deposited sample, a La–O super atomic layer structure was observed and La was in lower oxidation states as it diffused deeper into SiO2. The LaSiO thickness only increased slightly after post annealing and the gate stack showed the required thermal stability. All the results make TaN/LaSiO/Si a promising choice for transistor gate stacks. The combination of EELS mapping and other techniques is very useful in the chemical composition study of gate stacks at ultra-high spatial resolution.
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