Abstract
This paper presents a thorough description of the high-frequency noise characterization and modeling of CMOS transistors for radio frequency (RF) integrated circuit (IC) design. It covers two main topics: high-frequency noise characterization and physics-based noise models. In the first section, two de-embedding procedures are presented for noise and scattering parameter de-embedding to get rid of the parasitic effects from the probe pads and interconnections in the device-under-test (DUT). With the intrinsic noise parameters, two extraction methods to obtain the channel noise, induced gate noise and their correlation in MOSFETs are discussed and experimental results are presented. Based on the noise information obtained in the first section, the second part of the paper presents physics-based noise models for the noise sources of interest in deep submicron MOSFETs. It discusses the model derivation, channel noise enhancement in deep submicron MOSFETs and impact of channel length modulation (CLM) effect. Finally a simple and accurate analytical model for channel noise calculation will be presented.
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