Challenges in HF noise characterization and modeling of sub-100nm MOSFETs for RF ICs

Abstract

This paper presents the challenges in the high-frequency noise characterization and modeling of sub-100nm MOSFETs for radio-frequency (RF) integrated circuits (IC). In general, it addresses three major issues - accuracy of high-frequency (HF) noise measurements, impact of test structure designs and physics-based noise models for the noise sources of interest - channel noise, induced gate noise and gate tunneling noise. In the first section, different HF measurement techniques, namely Y-factor method and power-equation method are reviewed. The impact due to the difference in the output impedances of a noise source in the hot and the cold states on the measurement accuracy is demonstrated. In the second section, different test structures and de-embedding procedures for noise and scattering parameter de-embedding to get rid of the parasitic effects from the probe pads and interconnections in a device-under-test (DUT) are reviewed. Special considerations on the measurement accuracy are paid to the shift of DC bias conditions. Finally, with the power spectral densities for the noise sources of interest obtained from the intrinsic noise parameters, different physics-based noise models for these noise sources in sub-100nm MOSFETs are discussed. The impact of the channel-length modulation (CLM) effect, the hot electron effect and the velocity saturation effect on the channel thermal noise and the impact of the gate tunneling noise on the noise performance of deep submicron MOSFETs are reviewed.