Characterization and modeling of fast traps in thermal agglomerating germanium nanocrystal metal-oxide-semiconductor capacitor

Abstract

In this paper, the germanium (Ge) nanocrystals (NCs) are synthesized by using the rapid-thermal annealing and are embedded into a three-layer (SiO2∕NCs–Ge∕SiO2) capacitor structure. The samples with∕without the postmetallization annealing (PMA) treatment are investigated to compare and study the PMA affections. The charge storage characteristics of our samples are investigated with the capacitance-voltage (C-V) hystereses. The frequency independence of hysteresis windows is found and attributed to NCs as slow traps with a large characteristic time constant. The frequency-dependent C-V and conductance-voltage (G-V) experiments are further introduced to study the interface traps and the fast traps induced by the NC formation. In order to extract the related trap characteristics from the measured C-V and G-V, we propose to utilize the equivalent circuit and single-level trap model based on Shakley-Read-Hall theory. Three associated parameters including the areal trap density, trap conductance, and semiconductor capacitances are used to confirm that the single-level trap model is truly appropriate for our samples. It is then found from the model that the areal trap density is high and approaches almost uniform distribution along the valence band and bandgap but significantly reduced and then becomes decreased from valence band to the midgap after PMA treatment. In addition, after PMA treatment, the characteristic time constant becomes smaller for one order of magnitude at the same gate bias. It is attributed to the reduction of trap density and also agrees that the interface traps are dominant and has a small characteristic time constant.