Chapter Thirty Nine - Via Technologies for MEMS

Abstract

The main manufacturing techniques for through silicon vias (TSV) and through glass vias are presented in this chapter. Advanced packaging methods are needed to make miniaturized integrated devices containing chips that have been fabricated using various technologies. Wafer level 3-dimensional (3D) integration is an emerging technology where planar devices on wafers are stacked and interconnected using through wafer vias. The main drivers for 3D integration are better electrical performance, lower power consumption and noise, improvement of form factor, lower cost and increase of the functionality of a device. 3D integration is a hot research and development topic because of huge market potential for 3D stacking and heterogeneous integration of various materials and devices. An overview of TSV technologies is discussed in this chapter. The main obstacles for commercial implementation of MEMS devices are often related to packaging and inter-connection problems. Single Crystal Vias, Polycrystalline Silicon Vias and Metallic Vias are discussed in detail. The basics of laser ablation of silicon are also presented in this chapter.. It has been forecast that 3D vertical interconnects will revolutionize the whole 3D packaging and chip stacking. However, there still remains work to be done to achieve economically feasible and fast TSV processes. In MEMS, the challenges are related to process integration, stress control, and reliability. In RF-MEMS, the requirement for thick via insulation layer also poses challenges to the manufacturing.