Towards a Modeling Synthesis of Two or Three-Dimensional Circuits Through Substrate Coupling and Interconnections: Noises and Parasites

Abstract

The doubling of number of transistors in integrated circuits every two years, as stipulated by Moore’s law, has been the driving force for the huge development of microelectronics industry in the past 50 years. The Moore’s law has enabled the enhancement of complexity and density of planar integrated circuits in 2D of all functions on a single chip, resulting in the emergence of real system-on-chip (SOC). On the other hand, the integration of all these functions can be achieved through 3D integration. There are basically three types of 3D integration levels i.e. 3D IC packaging, 3D IC integration, and, 3D Si integration. These schemes are mostly different because the TSV (through-silicon via) applies to 3D IC and Si integrations, but not to 3D IC packaging. The use of TSV, with the new concept in which every chip or interposer could have two surfaces with circuits, is therefore at the heart of 3D IC and Si integration development. Continued technology scaling together with the integration of heterogeneous technologies on a single chip means that device performance should continue to outperform inter-connect and packaging capabilities, which rises several engineering challenges, such as power management, noise isolation, and intra and inter-chip communication. 3D Si heterogeneous integration is probably the right way to go in order to compete with Moore’s law in the frame of the so-called “more than Moore” application field. In this book, Prof. C. Gontrand aims at providing a modelling synthesis of two or three-dimensional circuits with emphasis on noise and parasitic accounting for substrate coupling and interconnections issues. In chapter 1, the author underlines that, when increasing interconnect densities and rising cost of integrated circuit (IC) manufacturing, 3D architectures for IC integration are a very promising alternative to standard 2D designs, and, that 3D technology is facing many technological challenges, like completion of vertical interconnects (TSV) which ensure the signal transmission, bonding with alignment of functional dies and substrate thinning. However, he is also noticing that a lot of benefits in circuit performances can be achieved by 3D integration. In chapter 2, the author is discussing on the generation of digital parasitics, their propagation through the substrate, and their effects on analogue devices. First, he is explaining how to characterize the substrate noise, in the time and frequency domains, in order to identify the major parameters that control substrate noise generation, propagation, and reception. Second, he is investigating the noise impact on analogue circuits from a circuit-level point of view. In chapter 3, the author is handling classical methods for noise analysis at a device point of view. They allow identifying a set of microscopic noise sources in terms of carrier velocity and population fluctuations - called diffusion and generation-recombination noise sources, respectively. Then, he is evaluating the effect of microscopic fluctuations on voltage or current fluctuations at the device terminals. In chapter 4, the author is dealing with propagation and radiative effects, which become more and more important in integrated circuits. Today deep submicron semiconductor devices are operated at very high frequencies (> GHz). This is particularly important for the characterization of interconnected structures loaded at digital and driver levels. Indeed, it is well known that electromagnetic compatibility (EMC) and signal integrity (SI) are strongly affected by the geometry of interconnects and by the possibly complex nonlinear/dynamic behaviour of the electronic devices located at their terminations. At this point, the author is undertaking a detailed semiconductor analysis based on the time-domain drift-diffusion model (DDM) in conjunction with electromagnetic model relying on Maxwell's equations. In the last chapter, the author demonstrates the effectiveness of such a modelling approach, which is validated in a wide frequency range from DC to 20 GHz. Nevertheless, at high frequency, he is showing that substrate-coupling effects are no more negligible and must be included in the overall 3D system electrical description. That is why the author is eventually proposing a substrate extraction method, based on transmission line method (TLM) or Green functions, to model the substrate network and interconnect entanglement. G. Ghibaudo PhD, IEEE senior member Director of research at CNRS (Grenoble, France)