Chapter 9 - Interrupt Control and System Control

Abstract

This chapter discusses various aspects of the Nested Vectored Interrupt Controller (NVIC) and System Control Block (SCB) features. The NVIC is an integrated part of the Cortex-M0 processor and is closely linked to the processor core logic and provides the functions of interrupt control and system exception support. The SCB contains features for operating system support, like an internal timer for the SysTick exception. The interrupt pending status can be accessed or modified through the Interrupt Set Pending (SETPEND) and Interrupt Clear Pending (CLRPEND) register addresses. The Cortex-M0 processor supports interrupt requests in the form of a level trigger as well as pulse input. The feature involves a number of pending status registers associated with interrupt inputs, including the nonmaskable interrupt (NMI) input. It is observed that if signal is connected to a 0, then the Cortex-M0 processor will start to process the interrupt request as soon as possible.