Chapter 6 - Hardware implementation of LDPC decoders

Abstract

This chapter explores alternative hardware architectures for fully-parallel and partially-parallel decoders for standard applications. The decoders use the low-complexity low density parity check (LDPC) algorithms and flexible parity check matrices presented in the previous chapters. The importance of designing hardware aware LDPC decoding algorithms and parity check matrices is also highlighted. The design methodology, automation techniques and simulation environment used in the hardware implementation process of these decoders is illustrated. The field programmable gate array (FPGA) emulation test setup is used for quick prototyping of the implemented decoder and for verifying practical performance, using various benchmarking metrics and parameters. A comprehensive description of the decoder architectures focusing on the area optimization and memory efficient features achieved in the hardware is presented. The FPGA implementation results of the decoders are compared with other standard and benchmarked results. A complete design space exploration for the decoder architectures in terms of decoding performance and hardware efficiency is discussed in later sections of this chapter.