Abstract
The '430 offers numerous interrupt sources, both external and internal. Interrupts are prioritized, with the reset interrupt having the highest priority. This chapter discusses the reset sources and conditions in detail, and describes the MSP430 interrupt functionality. The '430 uses two separate reset signals, one for hardware and one for software. The hardware reset, which is identified in the literature as power on reset (POR), is generated on initial power up and when the reset line (RST/NMI) is pulled low. Power up clear (PUC) can be forced from software by purposely writing security violations in either the Watchdog or Flash, or by neglecting to “pet the dog,” thereby allowing Watchdog expiration. Upon a reset signal (POR), the Status Register is reset, and the address in location 0FFFEh is loaded into the Status Register. Peripheral registers all enter their power up state with the peripheral register descriptions themselves.
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