Robust, self-timed power-on reset circuit for low-voltage applications

Abstract

The purpose of the Power-on Reset (POR) circuit is to reset the latches and flip-flops in an SOC to a known state when the supply is ramping up. During power-up, supply is not stable, and the ramp-up time can vary depending on the applications. A common approach is to generate a POR signal by comparing the supply voltage with a reference voltage. Conventional POR circuits also use a resistor divider circuit along with band gap reference. Low-power applications, like Internet of Things (IoT) devices, comprise of SRAM arrays, sensors, and logic operating at sub-threshold or extremely low voltages. At these low operating voltages, generating a stable reference voltage is difficult because of band gap reference limitations and process variations. In this paper, we present a POR circuit that operates without using a reference voltage, making it robust against different sources of variation. The proposed circuit is self-timed, meaning the reset signal pulse-width varies according to the time needed to reset the latch. The designed circuit has been fabricated in 16nm FINFET technology. Silicon validation shows that the proposed POR circuit works at a minimum supply voltage of 400mv. Simulation verifies that the POR circuit is operational in sub-threshold region, but is limited to 400mV on silicon due to the operational voltage of additional testchip logic. Also, the POR circuit does not consume any dynamic power during normal operation of the SOC and has minimal area overhead of 21.3pm2.