Chapter 3 - Basic Technology for Formal Verification

Abstract

The chapter reviews the essential concepts of the Boolean satisfiability (SAT) problem solvers, binary decision diagrams, and automatic test pattern generation (ATPG) solvers followed by a review of theorem-proving techniques and their related decision procedures from the viewpoint of their applications to formal, high-level design verification. The Davis Putnam Logemann-Loveland (DPLL) algorithm essentially performs a branch-and-bound search over the space of possible Boolean assignments to the variables of the given prepositional formula. It is a sound and complete algorithm—that is, it finds a satisfying assignment if and only if the given formula is satisfiable. Reduced ordered binary decision diagrams (ROBDDs) are a canonical representation for Boolean functions. For several Boolean functions of practical interest, ROBDDs provide a substantially more compact representation than other traditional alternatives such as truth tables, sum-of-products (SOP) forms, factored forms, or conjunctive normal form representations. ATPG is the process of generating a suite of test vectors that can be used for the purposes of testing a manufactured circuit for manufacturing faults. Manufacturing faults are physical defects introduced into the integrated circuit during the manufacturing process that result in its incorrect operation. In the current context, the only fault we will consider is one that causes a signal to be permanently stuck at a logical value 0 or 1 (or a defect that can, for all practical purposes, be modeled as such). Such a fault is called a stuck-at (0 or 1) fault.