Chapter 18 - Digital Simulation

Abstract

PSpice uses the same simulation engine for both analog and digital parts. Digital transistor–transistor logic (TTL) and complementary metal oxide semiconductor (CMOS) parts are modeled as subcircuits, and include the common digital functions, such as gates, registers, flip-flops, and inverters. Within each subcircuit, a digital primitive makes up the gate function and defines the timing and interface specification for the gate function. Other digital devices include delay lines, AtoD, digital to analog (DtoA), RAM, ROM, and programmable logic arrays. A model definition for a two-input CMOS NAND gate is given. Digital gates by default do not show their power supply pins because this would require a relatively large number of wires to connect all the gates to the power supply, which would overcomplicate the circuit. Instead, TTL and CMOS devices are connected to global power supply nodes, which are not displayed and by default are set to 5 V. Different power supplies can be set to accommodate the 13–18 V voltage supply range for CMOS devices. To set digital logic levels on integrated circuit (IC) pins, it is recommended to use digital HI and LO symbols. The Timing Mode option lets users select the minimum, typical, maximum, or the worst case timing characteristics for the digital devices. There is also the option to suppress simulation error messages, as PSpice reports any digital timing hazards or timing violations. Digital signals are shown as either high or low logic levels.