Chapter 15 - The Pulse Mode Approach to Asynchronous FSM Design

Abstract

This chapter illustrates asynchronous finite state machine (FSMs) that are designed to operate with nonoverlapping pulsed inputs and that use data-triggered memory elements called pulse mode sequential machines. The pulse-mode approach offers a simple and reliable means of designing clock-independent FSMs, but at the price of greatly restricted input signal conditions. Asynchronous FSMs are designed to operate in the fundamental mode. The fundamental mode is characterized, in part, by overlapping input signals and the potential to form certain types of timing defects such as endless cycles, critical races, and essential hazards, any of which, if present and active, is guaranteed to cause malfunction of the FSM. Fundamental mode FSMs can also cause malfunction due to the presence of static hazards in the NS-forming logic. However, like synchronous FSMs and unlike fundamental mode FSMs, properly designed pulse mode machines cannot have any of these timing defects—no endless cycles, no critical races, and no essential hazards. Furthermore, pulse mode FSMs cannot malfunction because of static hazards in the NS logic. Thus, pulse mode FSMs would seem to have all the advantages of synchronous FSMs, but with none of the timing defects of fundamental mode machines.