Chapter 14 - Memory Management Units

Abstract

This chapter begins with a review of the protection features of a memory protection unit (MPU) and then present the additional features provided by a memory management unit (MMU). It introduces relocation registers, which hold the conversion data to translate virtual memory addresses to physical memory addresses, and the Translation Lookaside Buffer (TLB), which is a cache of recent address relocations. It then explains the use of pages and page tables to configure the behavior of the relocation registers. It then discusses how to create regions by configuring blocks of pages in virtual memory. The overview of the MMU and its support of virtual memory ends by showing how to manipulate the MMU and page tables to support multitasking. Next the chapter presents the details of configuring the MMU hardware by presenting a section for each of the following components in an ARM MMU: page tables, the Translation Lookaside Buffer (TLB), access permission, caches and write buffer, the CP15:c1 control register, and the Fast Context Switch Extension (FCSE). The chapter ends by providing demonstration software that shows how to set up an embedded system using virtual memory.