Chapter 13 - Future trends in silicon technologies

Abstract

This chapter focuses on the advancements in silicon semiconductor technology that has primarily been driven by Moore's Law. This was enabled by lithographic device shrinks and the introduction of new materials for each new generation of devices. In addition, scaling of the planar complementary metal–oxide semiconductor (CMOS) transistor structure has allowed improvement in performance for the last 20 years. However, conventional planar CMOS device structure is fast approaching its scaling limits. New materials as well as new device structures are needed to alleviate the scaling issues. Two of the most important new materials being introduced are high and low dielectrics. Some of the new devices under investigation include silicon on insulator (SOI), strained Si, vertical CMOS transistors with double gate, and 3D integrated circuits (ICs). This chapter also examines the future trends in CMOS device technology, and the extension of CMOS scaling, for both high-performance logic and memory devices. Finally, it examines the implications of these new device structures on future processes and material requirements, with emphasis on dielectrics materials.