Channel design methodology for 28Gb/s SerDes FPGA applications with stacked silicon interconnect technology

Abstract

Bandwidth demand is exploding due to internet video/TV streaming, Web surfing, file sharing, VoIP, video calling, online gaming, and etc. The bandwidth requirement leads us to develop 400G line card solution for communication systems. 28Gb/s electrical interface can increase port density and reduce power per bit. New heterogeneous SSIT (Stacked Silcon Interconnect Technology) design to implement 28Gb/s SerDes transceivers into an FPGA package will be introduced. The silicon interposer was used in this technology and it includes a significant number of TSVs (Through Silicon Vias) for the high speed signals. It is imperative that the signal path including the interposer is accurately modeled over the high operating frequency range by considering all those requirements before design optimization. Detailed design optimization for interposer has been performed to evaluate optimum design rules by taking into consideration of manufacturability and the TSV's parasitic effects from DC to high frequency, which can cause major performance degradation. A package channel design methodology for 28Gb/s SerDes signal support will be introduced. The package material selection to minimize dielectric loss and trace design to minimize copper/surface roughness loss for package substrate are very important. In addition, the design topologies to minimize signal attenuation loss, reflection loss, crosstalk and power coupling noise will be presented. Package and PCB design co-optimization is very important to minimize reflections from solder ball interface. Any single mismatch in the very high speed system can result in the significant closer of the eye diagram. Once full channel analysis has been performed including optimized stacked silicon interposer model on top of low loss package substrate and PCB model, the simulation data is compared to the measured 28Gb/s Eye diagram and showing very good correlation. The proposed optimized channel system enables high performance signaling and great visibility of 28Gb/s Serdes FPGA applications.