Challenges and opportunity in performance, variability and reliability in sub-45 nm CMOS technologies

Abstract

In this paper, we present a detailed discussion related to the consequences on CMOS process flow for the high-speed race required by electronics applications. Key process elements for CMOS circuits speed enhancement are reported such as process stressors, high-k metal gate (HK/MG) stack, and low resistivity ultra-shallow junctions. Physical description and electrical interests are deeply discussed. Beside pure performance benefit, side effects of new process steps implementation are presented. Key transistor parameters variability as threshold voltage and drive current and reliability have been investigated for CMOS transistor. Finally a first risk evaluation is proposed for sub-28nm CMOS technologies with more aggressive architectures introduction.