Cascaded multilevel inverter using sub-multilevel cells

Abstract

The multilevel inverters have been in the center of focus of many researcher in recent years. This is partly because of some advantages such as improved output power quality. The multilevel inverters can generate a near sinusoidal output voltage. The quality of output voltage depends on the number of voltage levels of inverter. This paper proposes and analyses a generalized cascaded multilevel inverter topology with reduced switching devices. As the proposed topology is a general topology, it offers provisions to design a desired multilevel inverter. Also, the topology optimization of the proposed cascaded multilevel considering some factors such as number of switching devices, number of output voltage levels and the standing voltage on the switches is given. Also, considering the generality of the proposed multilevel inverter, the conventional cascaded H-bridge (CHB) multilevel inverters (both symmetric and asymmetric) can be derived form the proposed topology. In addition, some facts related to the conventional CHB topologies are proved mathematically. For instance it is proved that the trinary CHB topology is the best topology in the case of asymmetric condition. In order to verify the proposed topology, a 13-level inverter has been simulated and experimentally implemented.